# Computer Architecture **In a nutshell:** Let's recap the last four modules: we've built some elementary logic gates (module 1), and then used them to build an ALU (module 2) and a RAM (module 3). We then played with low-level programming (module 4), assuming that the overall computer is actually available. In this module we assemble all these building blocks into a general-purpose 16-bit computer called *Hack*. We will start by building the Hack Central Processing Unit (CPU), and we will then integrate the CPU with the RAM, creating a full-blown computer system capable of executing programs written in the Hack machine language. **Key concepts:** Von Neumann and Harvard architectures, the stored program concept, fetch-execute cycle, data bus, instruction bus, CPU, computer design. Unit 5.1: Von Neumann Architecture * The ALU loads information from the Data bus and manipulates it using the Control bits. * Both Data and Addresses are stored in the registers. ![](https://1094113337-files.gitbook.io/~/files/v0/b/gitbook-legacy-files/o/assets%2F-M3hoduT4ByoNaznkzhG%2F-MKfjBcTbOuKy-HGWJ-w%2F-MKfjs7i7rvJx9lOZGr-%2Fimage.png?alt=media\&token=61c22f95-d0e1-4836-ab84-dfb373133042) Unit 5.2: The Fetch-Execute Cycle ### Fetching * Put the location of the next instruction into the "address" of the program memory * Get the instruction code itself by reading the memory contents at that location ![](https://1094113337-files.gitbook.io/~/files/v0/b/gitbook-legacy-files/o/assets%2F-M3hoduT4ByoNaznkzhG%2F-MKfjvATjg7SETCF8-U5%2F-MKfrQOK7qfWep9KYs2G%2Fimage.png?alt=media\&token=9b07b718-0efe-4d2e-a002-d7d45ab49df0) ### Executing * The instruction code specifies "what to do" * Which arithmetic or logical instruction * What memory to access (read/write) * if/where to jump * ... * Often, different subsets of the bits control different aspects of the operation * Executing the operation involves also accessing registers and/or data memory ![](https://1094113337-files.gitbook.io/~/files/v0/b/gitbook-legacy-files/o/assets%2F-M3hoduT4ByoNaznkzhG%2F-MKfrnwf-YZWutBAVM8K%2F-MKfsMYLdd9bVPYs0Myw%2Fimage.png?alt=media\&token=cf69e4d2-2de8-4771-81bf-9e793a225065) ![](https://1094113337-files.gitbook.io/~/files/v0/b/gitbook-legacy-files/o/assets%2F-M3hoduT4ByoNaznkzhG%2F-MKfrnwf-YZWutBAVM8K%2F-MKfsVDGXwYdJGGDH2o8%2Fimage.png?alt=media\&token=ace0dbf0-14cc-4da2-ad7b-58cfdbbb8fe6) ![](https://1094113337-files.gitbook.io/~/files/v0/b/gitbook-legacy-files/o/assets%2F-M3hoduT4ByoNaznkzhG%2F-MKfsWIwctkVfXv4AX9X%2F-MKfsfOyM6UlcLFhALho%2Fimage.png?alt=media\&token=4c657ae4-ceb9-44f8-8f53-ee1029514f01) The fetch part of the cycle reads from the program memory, and the execute part reads from data memory. ### Simpler Solution: Harvard Architecture * Variant of von Neumann * Keeps Program and Data in two separate memory modules * Complication avoided ## Unit 5.3: Central Processing Unit * The Hack CPU Abstraction * a 16-bit processor designed to: * Execute the current instruction * Figure out which instruction to execute next (written in the Hack language) ![](https://1094113337-files.gitbook.io/~/files/v0/b/gitbook-legacy-files/o/assets%2F-M3hoduT4ByoNaznkzhG%2F-MKfsuTPY7n3q-qnUpgZ%2F-MKfuJJj0EJh9_t2879_%2Fimage.png?alt=media\&token=6f1a7d93-b361-4a7e-8645-b9bfaf4868a5) ![](https://1094113337-files.gitbook.io/~/files/v0/b/gitbook-legacy-files/o/assets%2F-M3hoduT4ByoNaznkzhG%2F-MKfsuTPY7n3q-qnUpgZ%2F-MKfulgWRj3pa8Orl6_g%2Fimage.png?alt=media\&token=f9287555-5590-4ef8-9770-0e98a08e63f2) ![](https://1094113337-files.gitbook.io/~/files/v0/b/gitbook-legacy-files/o/assets%2F-M3hoduT4ByoNaznkzhG%2F-MKfumwwYYQF0mh15Baf%2F-MKfv8oqJJGXcXbCB2Pj%2Fimage.png?alt=media\&token=f5cb17a6-ff36-4c37-928b-8a8789f2bafb) ![](https://1094113337-files.gitbook.io/~/files/v0/b/gitbook-legacy-files/o/assets%2F-M3hoduT4ByoNaznkzhG%2F-MKfumwwYYQF0mh15Baf%2F-MKfvJ2ITmSgJmphISYt%2Fimage.png?alt=media\&token=6cddb530-b8ab-4ba0-96e4-eabbaccd9f44) ![](https://1094113337-files.gitbook.io/~/files/v0/b/gitbook-legacy-files/o/assets%2F-M3hoduT4ByoNaznkzhG%2F-MKfvN9NrkAJ0Lb9rHkM%2F-MKfwydiOIVIQEw8fkCD%2Fimage.png?alt=media\&token=97da6c00-0cc1-4043-9f88-64e6a7341308) ![](https://1094113337-files.gitbook.io/~/files/v0/b/gitbook-legacy-files/o/assets%2F-M3hoduT4ByoNaznkzhG%2F-MKfvN9NrkAJ0Lb9rHkM%2F-MKfx55MwwNLhOIaE1OG%2Fimage.png?alt=media\&token=c1200363-6d00-4a9f-825c-400de75e5f11) ![](https://1094113337-files.gitbook.io/~/files/v0/b/gitbook-legacy-files/o/assets%2F-M3hoduT4ByoNaznkzhG%2F-MKfx7WV-N76452FnCzb%2F-MKg3keW7g4PG5-fghg9%2Fimage.png?alt=media\&token=f76b9ae0-a97d-4202-9780-ae866ad7d4f0) ![](https://1094113337-files.gitbook.io/~/files/v0/b/gitbook-legacy-files/o/assets%2F-M3hoduT4ByoNaznkzhG%2F-MKfx7WV-N76452FnCzb%2F-MKg444qQvVWUjFZLIhV%2Fimage.png?alt=media\&token=36adc416-b452-43fe-b60d-efa67aaad99f) Unit 5.4: The Hack Computer * Abstraction: A computer capable of running programs written in the Hack machine language. ![](https://1094113337-files.gitbook.io/~/files/v0/b/gitbook-legacy-files/o/assets%2F-M3hoduT4ByoNaznkzhG%2F-MKg46x-7zicvMIN1Bn4%2F-MKh7v0QmyPGe8uHpzev%2Fimage.png?alt=media\&token=f3ede16b-c6f8-4935-8abf-2aa9bd13ca1a) ![](https://1094113337-files.gitbook.io/~/files/v0/b/gitbook-legacy-files/o/assets%2F-M3hoduT4ByoNaznkzhG%2F-MKg46x-7zicvMIN1Bn4%2F-MKh88Ni1Ih35zVO2hdJ%2Fimage.png?alt=media\&token=e5af90f3-1a0f-47bf-903c-d22cbbe1b5ac) ![](https://1094113337-files.gitbook.io/~/files/v0/b/gitbook-legacy-files/o/assets%2F-M3hoduT4ByoNaznkzhG%2F-MKg46x-7zicvMIN1Bn4%2F-MKh8Ooij2IanzOfl6C9%2Fimage.png?alt=media\&token=4d43f988-7882-4f31-b484-334940be9f86) * RAM: 16-bit / 16K RAM chip * Screen: 16-bit / 8K memory chip with a raster display side-effect * Keyboard: 16-bit register with a keyboard side-effect * probe memory register 24576 ![](https://1094113337-files.gitbook.io/~/files/v0/b/gitbook-legacy-files/o/assets%2F-M3hoduT4ByoNaznkzhG%2F-MKh9Ld8oRSj8_5DFSE5%2F-MKh9V9YLrA1kKBRknTh%2Fimage.png?alt=media\&token=2312dde0-e571-4202-b553-e6ae22a66753) * Hardware implementation: plug-and-play ROM chips * Hardware simulation: programs are stored in text files; program loading is emulated by the built-in ROM chip ![](https://1094113337-files.gitbook.io/~/files/v0/b/gitbook-legacy-files/o/assets%2F-M3hoduT4ByoNaznkzhG%2F-MKh9Ld8oRSj8_5DFSE5%2F-MKhAMqnztEyUqsjDqy-%2Fimage.png?alt=media\&token=41cfaceb-7865-47ae-abb5-989119c28353) ![2 inputs](https://1094113337-files.gitbook.io/~/files/v0/b/gitbook-legacy-files/o/assets%2F-M3hoduT4ByoNaznkzhG%2F-MKh9Ld8oRSj8_5DFSE5%2F-MKhAkzw2HPEKRNzPVoe%2Fimage.png?alt=media\&token=e085e773-879b-42d4-bcab-e55960b830a9) Unit 5.5: Project 5 Overview ![](https://1094113337-files.gitbook.io/~/files/v0/b/gitbook-legacy-files/o/assets%2F-M3hoduT4ByoNaznkzhG%2F-MKhAtDrlVJamXx2uxAq%2F-MKhCIAca8ChHJpOMo_5%2Fimage.png?alt=media\&token=57ab4616-0deb-44ae-8c59-aef4742fd562) ![](https://1094113337-files.gitbook.io/~/files/v0/b/gitbook-legacy-files/o/assets%2F-M3hoduT4ByoNaznkzhG%2F-MKhAtDrlVJamXx2uxAq%2F-MKhCb_Con9T1u_RCfOk%2Fimage.png?alt=media\&token=a283aacb-c4c1-4439-b8c5-6743fb47a0dc)