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# Computer Architecture

**In a nutshell:** Let's recap the last four modules: we've built some elementary logic gates (module 1), and then used them to build an ALU (module 2) and a RAM (module 3). We then played with low-level programming (module 4), assuming that the overall computer is actually available. In this module we assemble all these building blocks into a general-purpose 16-bit computer called *Hack*. We will start by building the Hack Central Processing Unit (CPU), and we will then integrate the CPU with the RAM, creating a full-blown computer system capable of executing programs written in the Hack machine language.

**Key concepts:** Von Neumann and Harvard architectures, the stored program concept, fetch-execute cycle, data bus, instruction bus, CPU, computer design.

Unit 5.1: Von Neumann Architecture

* The ALU loads information from the Data bus and manipulates it using the Control bits.
* Both Data and Addresses are stored in the registers.

![](/files/-MKfjs7i7rvJx9lOZGr-)

Unit 5.2: The Fetch-Execute Cycle

### Fetching

* Put the location of the next instruction into the "address" of the program memory
* Get the instruction code itself by reading the memory contents at that location

![](/files/-MKfrQOK7qfWep9KYs2G)

### Executing

* The instruction code specifies "what to do"
  * Which arithmetic or logical instruction
  * What memory to access (read/write)
  * if/where to jump
  * ...
* Often, different subsets of the bits control different aspects of the operation
* Executing the operation involves also accessing registers and/or data memory

![](/files/-MKfsMYLdd9bVPYs0Myw)

![](/files/-MKfsVDGXwYdJGGDH2o8)

![](/files/-MKfsfOyM6UlcLFhALho)

The fetch part of the cycle reads from the program memory, and the execute part reads from data memory.

### Simpler Solution: Harvard Architecture

* Variant of von Neumann
* Keeps Program and Data in two separate memory modules
* Complication avoided

## Unit 5.3: Central Processing Unit

* The Hack CPU Abstraction
  * a 16-bit processor designed to:
    * Execute the current instruction
    * Figure out which instruction to execute next (written in the Hack language)

![](/files/-MKfuJJj0EJh9_t2879_)

![](/files/-MKfulgWRj3pa8Orl6_g)

![](/files/-MKfv8oqJJGXcXbCB2Pj)

![](/files/-MKfvJ2ITmSgJmphISYt)

![](/files/-MKfwydiOIVIQEw8fkCD)

![](/files/-MKfx55MwwNLhOIaE1OG)

![](/files/-MKg3keW7g4PG5-fghg9)

![](/files/-MKg444qQvVWUjFZLIhV)

Unit 5.4: The Hack Computer

* Abstraction: A computer capable of running programs written in the Hack machine language.

![](/files/-MKh7v0QmyPGe8uHpzev)

![](/files/-MKh88Ni1Ih35zVO2hdJ)

![](/files/-MKh8Ooij2IanzOfl6C9)

* RAM: 16-bit / 16K RAM chip
* Screen: 16-bit / 8K memory chip with a raster display side-effect
* Keyboard: 16-bit register with a keyboard side-effect
  * probe memory register 24576

![](/files/-MKh9V9YLrA1kKBRknTh)

* Hardware implementation: plug-and-play ROM chips
* Hardware simulation: programs are stored in text files; program loading is emulated by the built-in ROM chip

![](/files/-MKhAMqnztEyUqsjDqy-)

![2 inputs](/files/-MKhAkzw2HPEKRNzPVoe)

Unit 5.5: Project 5 Overview

![](/files/-MKhCIAca8ChHJpOMo_5)

![](/files/-MKhCb_Con9T1u_RCfOk)
